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Processor core speeds |
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1.30GHz, 1.20GHz, 1.10GHz, 1GHz, 950MHz, 900MHz, 850MHz and 800MHz (100MHz FSB), 766MHz, 733MHz, 700MHz, 667MHz, 633MHz, 600MHz, 566MHz, 533MHz, 533A MHz and 500MHz |
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Compatibility |
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Fully compatible with an entire library of PC software based on operating systems such as MS-DOS*, Windows* 3.1, Windows for Workgroups* 3.11, Windows 98, Windows 95, OS/2*, UnixWare*, SCO UNIX*, Windows NT, Windows 2000, OPENSTEP*, and Sun Solaris*. |
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Micro-architecture |
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P6 Dynamic Execution |
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System Bus |
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66 MHz or 100 MHz |
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Cache |
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Level 1 Cache: 32K (16K for infrastructure and 16K for data) Level 2 Cache: 128 KB Advanced Transfer Cache on frequencies 1.10 GHz and below. 256 KB Advanced Transfer Cache on the 1.20 GHz frequency parts |
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Motherboard |
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Compatible with the Intel® D810EMO, D810E2CA3, D810E2CB, D815BN, D815EEA2, D815EPEA2, D815EFV, D815EPFV, D815EEA, D815EPEA, D820LP, CC820, D810EMO, JN440BX, RC440BX, SE440BX(450 MHz only), SE440BX-2, SR440BX, CA810E. |
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Chipset |
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Compatible with the Intel® 815E chipset, 815 chipset, 815EP chipset, 815P chipset, 815G chipset, 815EG chipset |
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RAM |
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SDRAM |
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Packages |
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Single Edge Contact Cartridge 2 (S.E.C.C.2), Flip-Chip Pin Grid Array (FC-PGA) and Flip-Chip Pin Grid Array 2 (FC-PGA2) |
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Micron process technology |
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0.13 and 0.18 micron manufacturing processes |
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P6 Dynamic Execution Micro-architecture |
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Includes multiple branch prediction, data flow analysis, and speculative execution. |
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Multiple branch prediction |
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Predicts program execution through multiple branches, accelerating the flow of work to the processor. |
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Data flow analysis |
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Creates an optimized, reordered schedule of instructions by analyzing data dependencies between instructions. |
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Speculative execution |
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Carries out instruction execution speculatively, ensuring superscalar execution units remain busy, boosting overall performance. |
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Non-Blocking Level 1 Cache |
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Fast access to the recently used data, increasing the overall performance of the system |
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128 KB Level 2 Advanced Transfer Cache |
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Higher data bandwidth interface between the level 2 cache and the processor core reduces latency interface to cache data |
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Internet Streaming SIMD Extensions |
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Higher resolution images viewed and manipulated, high quality audio, MPEG2 video, and simultaneous MPEG2 encoding and decoding, reduced CPU utilization for speech recognition, as well as higher accuracy and faster response times |
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Dual Independent Bus (DIB) |
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Frees system bus from cache traffic, providing higher overall system bandwidth, improved system performance and scalability |
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Up to 100 MHz System Bus |
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Increases bandwidth availability, providing a performance boost for multi-tasking operating systems and multimedia applications |
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Intel® MMX™ Technology |
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Enhances the performance and quality of media-rich applications |
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† The information in this page is from Intel Official Website